For Immediate Release
December 9, 1997

GEORGIA TECH'S PACKAGING RESEARCH CENTER (PRC) ANNOUNCES SECOND YEAR INNOVATIONS IN ELECTRONIC PACKAGING

The Packaging Research Center (PRC), inaugurated in December 1994 at the Georgia Institute of Technology, has reported on 10 major technical innovations developed within the last year. The Center now offers extensive, fundamental packaging-related undergraduate and three dozen graduate courses, in addition to 15 short courses for industry professionals.

The largest and most comprehensive electronic packaging center in the United States, the PRC is jointly funded by the National Science Foundation (NSF) as an Engineering Research Center (ERC), the Georgia Research Alliance of the State of Georgia, the Defense Advanced Research Projects Agency, and 33 industry sponsors. The Center's goal is to develop the next generation of semiconductor packaging technologies beyond those presently under development in industry, thereby enabling more competitive electronic products and systems in the telecommunications, computer, consumer, aerospace, and medical industries. The Center involves 33 faculty from seven academic departments and the Georgia Tech Research Institute, as well as 200 graduate and undergraduate students.

The Center is now in its third year of an 11-year, NSF ERC funding cycle and is in the process of setting up $30 million worth of world class prototype integration facilities that will demonstrate the next generation of system technologies.

The following innovations are described below:

• No Flow Underfill Material & Process Reduces Manufacturing Costs
• Modeling Process Provides Fast, Accurate Predictions in Circuit Behavior
• Novel In-Situ Monitoring Technique for Via Formation Using a Surface Micromachined Sensor
• New Coplanar Waveguide Probe Measures Properties of Ultra-Thin Materials
• Vertical Interconnect Package Provides Inexpensive Way to Maintain Signal Integrity
• Low-Cost Electronics for Automated At-Speed MCM Test
• Low-Cost, Massively-Parallel Test for MCM Substrates
• New Microjet Allows for Easy Integration into Electronic Devices
• New Tool Analyzes Simultaneous Switching Noise
• Fully Integrated MCM-L Module with Built-in Capacitors, Inductors, and Resistors

MEDIA RELATIONS CONTACTS: John Toon (404-894-6986); Fax: (404-894-1826); Internet: john.toon@edi.gatech.edu or Jackie Nemeth (404-894-2906); Fax: (404-894-4641); Internet: jackie.nemeth@ece.gatech.edu

TECHNICAL CONTACTS: Dr. Rao R. Tummala, director, Packaging Research Center, (404-894-9097); Internet: rao.tummala@ece.gatech.edu or Dr. Carl A. Rust, assistant director, Packaging Research Center, (404-894-3843); Internet: carl.rust@ece.gatech.edu

WRITER: Jackie Nemeth

NEW TECHNIQUE REDUCES COST OF MANUFACTURING PROCESSING

Researchers in the PRC's assembly thrust area have developed a novel, no flow underfill material and process that eliminates long underfilling and curing process times, significantly reducing flip-chip manufacturing cost; it also provides for throughputs compatible with surface mount assembly.

Led by Dr. Daniel F. Baldwin, assistant professor in the Woodruff School of Mechanical Engineering and Dr. C.P. Wong, professor in the School of Materials Science and Engineering, the PRC teams created this new, no flow assembly process and material, and Wong's group has filed two U.S. patents in this materials invention.

"The process and material contain a self-fluxing agent and a latent catalyst that eliminates the flip-chip fluxing, cleaning, and long underfilling and curing times," Wong said. "It simultaneously reflows and cures the solder joints and underfill using a conventional surface mount reflow furnace."

According to Baldwin, conventional underfill flow lasts from 15 seconds to 30 minutes, depending on the material, die size, and temperature. Curing commercially available underfill materials takes 1 to 2 hours and involves several time-consuming cleaning steps prior to underfill application.

In contrast, the no-flow underfills flow simultaneously with chip placement, typically 0.5 to 5 seconds, and the cycle times during cure and reflow last 3 to 5 minutes. Additionally, this process allows for interconnect testing and flip-chip repair, prior to the high value-added solder reflow joining process.

"Our analysis of the cost and processing times indicates a 2 to 6-fold reduction in assembly cost and at least a 50 percent reduction in processing cycle time over conventional flip-chip processing," Baldwin said. "Once the no flow underfill has been printed onto the organic substrate, and the flip-chip is placed piercing the underfill, the assembly is reflowed, forming the solder interconnects and curing. No further post-curing of the underfill is required."

TECHNICAL CONTACTS: Daniel F. Baldwin, assistant professor, Woodruff School of Mechanical Engineering, (404-894-4135), daniel.baldwin@me.gatech.edu and C.P. Wong, professor, School of Materials Science and Engineering, (404-894-8391), cpwong@ms-mail.chemse.gatech.edu

MODELING PROCESS PROVIDES FAST, ACCURATE PREDICTIONS IN CIRCUIT BEHAVIOR

New technologies and processes are becoming available to allow for screen printing and depositing 2- and 3-dimensional versions of resistors, inductors, and capacitors in spaces that are linewidths on the order of microns and are in many layers that are separated by distances as small as 100 microns or less. These technologies will allow for the creation of hidden passive component circuits, or a new generation of passive component integrated circuits, with the possibility of integrating an entire radio circuit in a single electronic package. These circuits will be smaller, require lower power, have higher reliability, and cost considerably less.

The current bottleneck for the progress of this technology is accurate, high speed modeling techniques. The physical nature of these structures requires that electromagnetic modeling methods be utilized; however, complex designs can result in simulation times and memory requirements that are enormous and impractical.

Associate Professor Dr. Martin Brooke and Graduate Research Assistant Ravi Poddar, both of the School of Electrical and Computer Engineering (ECE), are developing a new modeling technique based upon experimentally characterizing small fundamental blocks that make up a geometrical structure and then combining all the models of the various building blocks to obtain a prediction of the behavior of a larger structure. Brooke and Poddar construct equivalent circuits of the passive components, and by using these circuit simulations, they obtain high frequency predictions of electrical behavior.

The method has been experimentally shown to produce accurate results well past the first self-resonance frequency of the structure, generally up to the 10-20 GHz frequency range, according to Brooke and Poddar. In terms of speed, the method is orders of magnitude faster than traditional methods, such as finite element analysis or the method of moments. As an example, a spiral inductor simulated on a Sun workstation using a method of moments solver required over four hours of simulation time.

In contrast, performing the same simulation using the new modeling technique needed under two minutes -- 100 times faster than using the traditional methods. "In short, we believe this method could be the key to unlocking the full potential of the various new integration technologies, and allow us to proceed to new levels of system integration and miniaturization," according to Brooke.

TECHNICAL CONTACTS: Martin A. Brooke, associate professor, (404-894-3304), martin.brooke@ece.gatech.edu and Ravi Poddar, graduate research assistant, (404-894-5294), poddar@azalea.mirc.gatech.edu. Both are affiliated with the School of ECE.

A NOVEL IN-SITU MONITORING TECHNIQUE FOR VIA FORMATION USING A SURFACE MICROMACHINED SENSOR

In its pursuit of high yield multichip module manufacturing on large area substrates, one of the strategies of the PRC's Intelligent Large Area Manufacturing thrust team is to utilize novel microsensor technology for process monitoring. Associate Professor Dr. Gary S. May and his graduate student, Michael D. Baker, both of the School of Electrical and Computer Engineering (ECE), have developed a novel technique for monitoring film thickness in plasma etching, a critical process for the plasma de-scum step, which occurs at the conclusion of via formation using photosensitive polymer dielectrics.

May said that the plasma de-scum step is crucial to insure that the via is fully opened. If the via is not properly "de-scummed," the residue that remains after the via has been exposed can increase the resistivity of the connection between the metal layers. "This new sensor provides an easier, more efficient, more precise, and cheaper way to monitor the progress and quality of the fabrication of devices," he said. "It allows direct, non-intrusive, and real-time measurement of each etch rate. Other techniques cannot give you all three of these qualities simultaneously."

The prototype sensor correlates film thickness with the change in resonant frequency that occurs in a micromachined platform during etching. The platform is suspended over a drive electrode on the surface of the substrate and electrically excited into resonance. As material is etched from the platform, its resonant vibrational frequency shifts by an amount proportional to the amount of material etched, allowing the etch rate to be inferred.

As a proof-of-concept experiment, researchers fabricated a platform made of DuPont 2611 polyimide. The sensor was driven into resonance electrostatically, and the shift in resonance was detected by monitoring the change in impedance between the drive electrode and platform as the drive frequency is swept. To enhance filtering of the sensor signal in the noisy plasma environment, the platform is designed so that the ratio of the plasma frequency to the fundamental mode of vibration is approximately 400:1. The prototype was etched in a Plasma Therm 700 series etching system in a CHF3/O2 plasma. Electrical contact was made with the sensor using a feed-through attached to the vacuum line beneath the process chamber to facilitate in-situ excitation and measurement.

"This experiment demonstrated for the first time a real-time measurement of etch rate during plasma etching," May said. "The sensor was shown to offer high resolution (approximately 1300 Hz/micron) and a near linear correlation between film thickness and resonant frequency. Ultimately, this monitoring technique has the potential of providing in-situ process monitoring of both etch rate and uniformity at a nominal cost."

TECHNICAL CONTACT: Gary S. May, associate professor, School of ECE, (404-894-9420), gary.may@ece.gatech.edu

NEW PROBE MEASURES PROPERTIES OF ULTRA-THIN MATERIALS

Dr. Joy Laskar, an assistant professor in the School of Electrical and Computer Engineering (ECE), and his wireless electronics team have created a novel material coplanar waveguide probe (MCPW) for measuring material properties of thin material substrates. The MCPW -- a second generation, non-destructive technique for testing materials less than 1 centimeter -- was developed by Laskar's PRC team in collaboration with Cascade Microtech and the National Institute of Standards and Technology (NIST).

Typical material characterization techniques used to determine the dielecric properties of bulk materials usually include an open-ended coaxial line, a cavity resonator technique, and a transmission line technique. According to Laskar, using these devices on thinner materials would be destructive because they are meant for material substrates that are thicker than 1 centimeter and that possess lower throughput measurements. Therefore, technological advances in high density microwave packaging will require the use of multi-layer thin-film dielectrics such as the MCPW.

The probe, which serves as a transmission structure, is placed in intimate contact with a substrate under test using micro manipulators that are akin to conventional microwave probe concepts. Various transmission structures can be incorporated into the probe which allows researchers to extract information about the probe/material interface, and subsequently, the substrate material properties.

The PRC and its industrial partners are studying the application of embedded passive components for next generation wireless functions. "It is critical that these multilayer thin- film components be characterized as a function of frequency," Laskar said. "The MCPW probe has the potential to serve an important method to study such structures."

The second generation MCPW probe has been designed to incorporate the latest calibration procedures developed at NIST.

"We are currently developing calibration algorithms for multilayer ceramic structures," Laskar continued. "No alternative exists today and it may be applicable to electronic materials in addition to packages."

TECHNICAL CONTACT: Joy Laskar, assistant professor, School of ECE, (404-894-5268), joy.laskar@ece.gatech.edu

VERTICAL INTERCONNECT PACKAGE PROVIDES INEXPENSIVE WAY TO MAINTAIN SIGNAL INTEGRITY

As consumer electronics continually utilize higher and higher operating frequencies for personal communications, low-cost microwave packages become a major concern. Traditional microwave packages, well suited for high performance and low volume applications, are expensive and are often not well suited for mass production. Plastic surface mount packages are adequate for components operating below 5 GHz, but they do not meet the performance needs of microwave/millimeter-wave applications.

To meet the consumer electronic needs of the near future, Dr. Joy Laskar, assistant professor in the School of Electrical and Computer Engineering (ECE), and his wireless electronics team have designed a low-cost microwave package by leveraging current plastic package technologies, but modifying the physical footprint. This low-cost, shielded vertical interconnect package (VIP) has been engineered in collaboration with Hewlett-Packard to maintain RF signal integrity.

"The surface mount package footprint has been redesigned to provide near waveguide-like properties with the potential for operation to millimeter wave frequencies," Laskar said. "The initial VIP prototype has been designed, fabricated, and characterized and represents a significant breakthrough for low cost microwave packaging." His team has measured a 10 dB improvement in return loss with a non-optimized design, resulting in improved signal to noise ratios.

Continuing research in Laskar's group includes investigation of practical limitations of shielded vertical interconnect approaches suitable for integrated circuit and multichip module packaging in the microwave and millimeter-wave frequency range.

TECHNICAL CONTACT: Joy Laskar, assistant professor, School of ECE, (404-894-5268), joy.laskar@ece.gatech.edu

LOW-COST ELECTRONICS FOR AUTOMATED AT-SPEED MCM TEST

The vast majority of "functional" integrated circuit test systems used today operate at clock and data rates below 200 MHz. To meet this need, automated test equipment (ATE) manufacturers provide a wide variety of test systems with different pattern depths, different sequencing capabilities, different accuracies, and different throughput capabilities. The incremental cost per channel for large, 256-pin systems varies from about $2,000/channel to as much as $8,000-$10,000/channel. Therefore, the typical, 256-pin ATE system cost ranges from just under $1 million to as much as $3 million.

Judicious elimination of unused or rarely used features in existing test systems can leave room for substantial cost savings in future automated testers while still providing higher performance in the critical areas of clock rate, pin count, and pattern depth. This concept, called reduced instruction set test (RIST), utilizes commercially-available components.

Researchers in the systems, design, and test area of the PRC, led by Associate Professor Dr. David C. Keezer, of the School of Electrical and Computer Engineering, have developed and tested prototype electronics modules for low-cost testing at data rates exceeding 2.5 Gbps within a multi-channel, automated test environment. High-performance, emitter-coupled logic (ECL) is used to produce programmable multi-gigabit-per-second data streams with picosecond timing resolution. These are used as direct stimuli for testing or can be used to drive variable-level "drivers" when logic levels other than ECL are required.

The signals are synchronized with the operation of an automated test system (a Hewlett Packard model HP83000) which provides slower signals (up to 666 MHz) and a programmable test environment. For stimuli, the logic transitions occur in about 100 ps and are accurate to within +/-25 ps. Complementary logic circuits have also been developed, which can capture the test response at rates above 2.5 Gbps.

TECHNICAL CONTACT: David C. Keezer, associate professor, School of ECE, (404-894-4741), david.keezer@ece.gatech.edu

LOW-COST, MASSIVELY-PARALLEL TEST FOR MCM SUBSTRATES

PRC researchers, led by ECE's Dr. David C. Keezer, have developed a method for economically testing and diagnosing interconnect networks within MCM substrates. By applying a unique digital sequence to each interconnect net and monitoring the response at all nodes, shorts-to-ground, shorts-to-power, bridging shorts, and open-line faults are readily identified and diagnosed. The digital nature of the method allows for very economical test system implementation. In a test configuration with several thousand channels, the hardware cost will be on the order of a few dollars per channel. In addition to the low instrumentation cost, the approach significantly reduces test time and increases throughput.

Current methods utilize a movable probe for measuring interconnect capacitance or resistance. "The standard method is therefore time-consuming, possibly requiring many minutes of test time per substrate," Keezer said. "The new approach applies the entire test in a fraction of a second so that device handling is the limiting factor for throughput and not the test time."

A prototype system is now under development; it utilizes low-cost programmable gate arrays as the primary component, repeated throughout the test system. The largest remaining obstacle is the relatively high cost for high-density parallel probing mechanisms.

TECHNICAL CONTACT: David C. Keezer, associate professor, School of ECE, (404-894-4741), david.keezer@ece.gatech.edu

NEW MICROJET ALLOWS FOR EASY INTEGRATION INTO ELECTRONIC DEVICES

In the past year, the PRC thermal management team, led by Dr. William Z. Black, has perfected a new microjet in which synthetic microjet technology is taken to new levels of efficiency.

In the new design, the jet flows tangentially over the heat source and substantially modifies the thermal boundary layer and enhances the convective heat transfer. "This allows for the jet hardware to be installed in a flat, low-profile package that is adjacent to the cooled, integrated circuit package, and thus it can be easily integrated into tight spaces," Black said. Initial test data using the new slot-jet design has shown an increased rate of heat removal compared to normal microjet impingement.

About three years ago, the PRC thermal management thrust group introduced a novel cooling technique that utilizes synthetic air microjets to effectively cool both single packages and multi-chip modules. Microjets have proven to effectively cool individual chips, and they can also be interconnected to provide cooling for multiple packages. Synthetic jets can be manufactured using micro-fabrication technology and have several attributes that make them natural candidates for replacing traditional fans in a broad range of applications.

Black said that these attributes include low cost, small footprint, operation without the need for external plumbing, low power consumption, and high reliability. "Synthetic jets have been tested in both open- and closed-flow systems," he said. "For example, a microjet installed in a sealed enclosure of a cellular phone can reduce the operating temperature of the power amplifier by up to 40 percent."

TECHNICAL CONTACT: Ari Glezer, associate professor, Woodruff School of Mechanical Engineering, (404-894-3266), ari.glezer@me.gatech.edu and William Z. Black, Regents' professor, Woodruff School of Mechanical Engineering, (404-894-3257), william.black@me.gatech.edu

NEW TOOL ANALYZES SIMULTANEOUS SWITCHING NOISE

Electrical noise generated by simultaneous switching drivers is a major concern when designing high performance CMOS ASIC (complementary metal-oxide semiconductor, application specific integrated circuits) logic families. If noise is uncontrolled, it can cause logic circuits to falsely switch states or cause an increase in circuit delay. Propagation of power distribution resonance noise is also a major concern for high speed digital and mixed signal packages.

The PRC computer-aided design (CAD) group, led by Dr. Madhavan Swaminathan, has developed a new prototype tool that predicts noise using a methodology that is different from existing CAD tools by incorporating the interaction between the chip, package, and printed circuit board. The tool, which has been validated using a Motorola test board, uses sub-circuit SPICE (software process improvement and capability determination) models as the basic building blocks. They are then integrated to develop a distributed system level model for simultaneous switching noise analysis.

"This prototype tool is unique because it includes the interaction between the chip, package, and printed circuit board during modeling at an early design phase," Swaminathan said. "This methodology allows for the accurate prediction of noise at the system level since all the noise generating parasitics are included in the model. This is extremely important as chip sizes become larger since larger parasitics are contributed by the chip at the system level. Moreover, second order effects such as resonance, which is generated by the interaction between the chip and package, are captured accurately. Most of these effects are often ignored in present CAD tools."

Swaminathan and his team are currently using a similar prototype tool to predict noise on applications from Sun Microsystems. This technique -- to be implemented on Sun products containing high input-output, high performance flip-chip ball grid array packages -- was developed by Joshua LeVasseur, a recent B.E.E. graduate of Georgia Tech who now works at Intel, and Graduate Research Assistants Anand Haridass and Kumaresh Bathey, who now work with IBM.

TECHNICAL CONTACT: Madhavan Swaminathan, associate professor, School of Electrical and Computer Engineering, (404-894-3340), madhavan.swaminathan@ece.gatech.edu

FULLY INTEGRATED MCM-L MODULE WITH BUILT-IN CAPACITORS, INDUCTORS, AND RESISTORS

Integration of passive elements (resistors, capacitors, and inductors) provides numerous advantages such as improved electrical performance, reduced assembly cost, and improved packaging efficiency. However, this technology is yet to be developed for the low temperature fabrication process compatible to MCM-L technology.

At Georgia Tech, a low cost and fully integrated passive module has been fabricated for the first time utilizing the low temperature PWB compatible fabrication process. The passive RLC module includes 12 integrated resistors (5 to 80 ohms), four capacitors (14 to 160 pF), and four inductors (145 to 650 nH). The integrated resistors were patterned with evaporated metal (low temperature screen printing process is currently being evaluated), the capacitor dielectric was fabricated using a low cost photodefinable epoxy filled with higher dielectric constant (~17800 in sintered form) and finer (~1 micron size) ferroelectric ceramic powder, and the inductors used a nickel-zinc ferrite powder/polyimide composite. Spin coating and screen printing technology were utilized for the fabrication of capacitors and inductors. The inductors were protected with an EMI shielding material. The dimension of the RLC module is 10 mm x 8 mm x 0.07 mm.

According to Drs. Tummala and Mark G. Allen, both of the School of Electrical and Computer Engineering (ECE), the fabrication technology was relatively inexpensive and PWB compatible. "The use of epoxy could further reduce the overall material cost," Tummala and Allen said. "The module was electrically tested and the measured component values were comparable with the desired values."

TECHNICAL CONTACTS: Rao R. Tummala, director of the Packaging Research Center, (404-894-9097), rao.tummala@ece.gatech.edu and Mark G. Allen, associate professor, (404-894-9419), mark.allen@ece.gatech.edu Both are affiliated with the School of ECE.

NOTE: Additional information in the form of technical papers is available for most of the projects described in this bulletin. Images are also available for many of the items. For additional information, please contact either John Toon or Jackie Nemeth at the telephone numbers or e-mail address shown in the first section of this document.

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